Pre-Silicon ASIC Verification: Things Are Broken Till Verified!
“We need this ASIC to work from the word go… no more unplanned silicon spins.”
If you are from the semiconductor industry, there are good chances that you have heard this phrase often. As a product line manager (PLM) or a business unit (BU) manager, you would know how important it is for a company to get the ASIC right first time with at least all planned features.
Statistics show that companies lose millions of dollars due to and bugs in semiconductor leading to unplanned ASIC revisions. According to Mentor & Wilson Research Group, the percentage of IC/ASIC design project time spent in verification has gone up to an average of 55% between 2012 and 2018. Additionally, between 2007 and 2018, the average peak number of verification engineers vs. design engineers on a project has increased from 50% to 100% or in some cases even more than 100%, depending on the complexity of the chip.
Silicon design and verification teams require expert resources and time. While the two groups operate independently on the timeline, they heavily rely on each other for their deliverables. And this interdependency makes it even more challenging to push one team without impacting the other. Perhaps, an even more significant challenge in design and verification is creating a balance between productivity and engineering headcount.
Ensuring that the teams are not missing critical aspects of the development process and still meeting the timeline is a tightrope walk.
Costs of Inadequate or Improper Verification
Industry research and expert interviews have shown that semiconductor companies typically skimp on the time spent in verification planning. They focus their verification resources primarily on executing the project and staying on schedule, which leaves less time for proactive critical planning. Consequently, they may not be able to utilize opportunities for cost reduction and production efficiencies that could come from individual bits of intellectual property or simplified chip architectures.
With continuous consolidation of the semiconductor industry, controlling costs for positive impact on the operating margins is critical. Not to forget, getting the chip right and making it into customer circuits, beating the competition, in time, means so much to the top-line revenue! Nobody would want unplanned revisions of the chip due to those scary bugs because these could be pretty expensive. They inflate costs through:
Best Practices in Silicon Verification
Semiconductor firms can avoid high costs and losses by verifying the silicon chips correctly the first time. The right approach for the verification process is guided by best practices that involve thorough planning and methodical execution with full attention to details and closure. The steps to follow here are:
Things are Broken Until Verified
Pre-silicon semiconductor verification, both digital and mixed-signal, is one of the most complex disciplines, but when executed with the right approach, it helps companies significantly save time, costs, and resources. In essence, semiconductor verification must start with a mindset: “things are broken until verified.”
And it is essential to remember that a well-documented requirement specification with requirement IDs mapped is fundamental to the silicon verification. When a robust specification document is not in place, STOP! Fix that first!
At Cyient, we understand the need to get silicon right the first time and have more than two decades of experience in ASIC verification process. We work collaboratively with our clients to help them meet their goals in this industry, which is why seven out of ten global semiconductor companies work with us.
Click here to learn more about the process and make the difference to your operations.
By Vivek Kangralkar | July 24th, 2019